Publications

Journal articles

  • M. Sauer, A. Czutro, T. Schubert, S. Hillebrecht, I. Polian and B. Becker, “SAT-based Analysis of Sensitisable Paths,” IEEE Design & Test of Computers, 2013.
  • A. Czutro, I. Polian, M. Lewis, P. Engelke, S.M. Reddy and B. Becker, “Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability Analysis,” International Journal of Parallel Programming, vol. 38, pp. 185–202, June 2010.
  • Polian, A. Czutro, S. Kundu and B. Becker, “Power Droop Testing,” IEEE Design & Test of Computers, vol. 24, pp. 276–284, May 2007.

Dr. Alexander Czutro

Books

  • Alexander Czutro, “Efficiency and Applications of SAT-Based Test Pattern Generation — Complex fault models and optimisation problems,” Der Andere Verlag, ISBN 978-3862473885, November 2013.

Papers in formal proceedings (refereed)

  • M. Sauer, I. Polian, M.E. Imhof, A. Mumtaz, E. Schneider, A. Czutro, H.-J. Wunderlich and B. Becker, “Variation-Aware Deterministic ATPG,” in IEEE European Test Symposium, May 2014.
  • A. Czutro, I. Polian, S.M. Reddy and B. Becker, “SAT-Based Test Pattern Generation with Improved Dynamic Compaction,” in International Conference on VLSI Design, January 2014.
  • A. Czutro, M. Imhof, J. Jiang, A. Mumtaz, M. Sauer, B. Becker, I. Polian and H.-J. Wunderlich, “Variation-Aware Fault Grading,” in IEEE Asian Test Symposium, pp. 344–349, November 2012.
  • M. Sauer, A. Czutro, I. Polian and B. Becker, “Small-Delay-Fault ATPG with Waveform Accuracy,” in International Conference on Computer-Aided Design, pp. 30–36, November 2012.
  • M. Sauer, S. Kupferschmid, A. Czutro, I. Polian, S.M. Reddy and B. Becker, “Functional Test of Small-Delay Faults using SAT and Craig Interpolation,” in International Test Conference, pp. 1–8, November 2012.
  • L. Feiten, M. Sauer, T. Schubert, A. Czutro, E. Böhl, I. Polian and B. Becker, “#SAT-Based Vulnerability Analysis of Security Components — A Case Study,” in International Symposium on Defect and Fault Tolerance, October 2012.
  • A. Czutro, M. Sauer, I. Polian and B. Becker, “Multi-Conditional SAT-ATPG for Power-Droop Testing,” in IEEE European Test Symposium, May 2012.
  • M. Sauer, A. Czutro, B. Becker and I. Polian, “On the Quality of Test Vectors for Post-Silicon Characterization,” in IEEE European Test Symposium, May 2012.
  • A. Czutro, M. Sauer, T. Schubert, I. Polian and B. Becker, “SAT-ATPG Using Preferences for Improved Detection of Complex Defect Mechanisms,” in VLSI Test Symposium, April 2012.
  • J. Jiang, M. Sauer, A. Czutro, B. Becker and I. Polian, “On the Optimality of K Longest Path Generation Algorithm Under Memory Constraints,” in Conference on Design, Automation and Test in Europe, pp. 418–423, March 2012.
  • M. Sauer, S. Kupferschmid, A. Czutro, S.M. Reddy and B. Becker, “Analysis of Reachable Sensitisable Paths in Sequential Circuits with SAT and Craig Interpolation,” in International Conference on VLSI Design, January 2012.
  • M. Sauer, J. Jiang, A. Czutro, I. Polian and B. Becker, “Efficient SAT-Based Search for Longest Sensitisable Paths,” in IEEE Asian Test Symposium, November 2011.
  • M. Sauer, A. Czutro, I. Polian and B. Becker, “Estimation of Component Criticality in Early Design Steps,” in IEEE International On-line Testing Symposium, pp. 104–110, July 2011.
  • M. Sauer, A. Czutro, T. Schubert, S. Hillebrecht, I. Polian and B. Becker, “SAT-Based Analysis of Sensitisable Paths,” in IEEE Design and Diagnostics of Electronic Circuits and Systems, pp. 93–98, April 2011. Best Paper Award in the Test Category.
  • A. Czutro, I. Polian, P. Engelke, S.M. Reddy and B. Becker, “Dynamic Compaction in SAT-Based ATPG,” in IEEE Asian Test Symposium, November 2009.
  • M. Hunger, S. Hellebrand, A. Czutro, I. Polian and B. Becker, “ATPG-Based Grading of Strong Fault-Secureness,” in IEEE International Online Testing Symposium, June 2009.
  • N. Houarche, A. Czutro, M. Comte, P. Engelke, I. Polian, B. Becker and M. Renovell, “An Electrical Model for the Fault Simulation of Small-Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects,” in VLSI Test Symposium, April 2009.
  • A. Czutro, I. Polian, M. Lewis, P. Engelke, S.M. Reddy and B. Becker, “TIGUAN: Thread-parallel Integrated test pattern Generator Utilizing satisfiability ANalysis,” in International Conference on VLSI Design, pp. 227–232, January 2009.
  • A. Czutro, N. Houarche, P. Engelke, I. Polian, M. Comte, M. Renovell and B. Becker, “A Simulator of Small-Delay Faults Caused by Resistive- Open Defects,” in IEEE European Test Symposium, pp. 113–118, May 2008.
  • I. Polian, A. Czutro, S. Kundu and B. Becker, “Power Droop Testing,” in International Conference on Computer Design, pp. 243–250, October 2006.
  • I. Polian, A. Czutro and B. Becker, “Evolutionary Optimization in Code-Based Test Compression,” in Conference on Design, Automation and Test in Europe, pp. 1124–1129, March 2005.

Workshop contributions (refereed)

  • L. Feiten, M. Sauer, T. Schubert, A. Czutro, V. Tomashevich, E. Böhl, I. Polian and B. Becker, “#SAT for Vulnerability Analysis of Security Components,” in IEEE European Test Symposium (informal proceedings), May 2013.
  • A. Czutro, M. Sauer, I. Polian and B. Becker, “Multi-Conditional ATPG using SAT with Preferences,” in GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, February 2012.
  • M. Sauer, S. Kupferschmid, A. Czutro, I. Polian, S.M. Reddy and B. Becker, “Functional Justification in Sequential Circuits using SAT and Craig Interpolation,” in GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, February 2012.
  • J. Jiang, M. Sauer, A. Czutro, B. Becker and I. Polian, “On the Optimality of K Longest Path Generation,” in Workshop on RTL and High Level Testing, November 2011.
  • A. Czutro, B. Becker and I. Polian, “Performance Evaluation of SAT-Based ATPG on Multi-Core Architectures,” in IEEE East-West Design & Test Symposium, September 2009.
  • M. Hunger, S. Hellebrand, A. Czutro, I. Polian and B. Becker, “Robustheitsanalyse stark fehlersicherer Schaltungen mit SAT-basierter Testmustererzeugung,” in GMM/ITG-Fachtagung “Zuverlässigkeit und Entwurf”, September 2009.
  • A. Czutro, B. Becker and I. Polian, “Performance Evaluation of SAT-Based Automatic Test Pattern Generation on Multi-Core Architectures,” in GI/ITG International Conference on Architecture of Computing Systems, Many-CoresWorkshop, March 2009.
  • N. Houarche, A. Czutro, M. Comte, P. Engelke, I. Polian, B. Becker and M. Renovell, “Deriving an Electrical Model for Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects,” in Latin-American Test Workshop, March 2009.
  • A. Czutro, B. Becker and I. Polian, “Performance Evaluation of SAT-Based ATPG on Multi-Core Architectures,” in GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, February 2009. Poster.
  • A. Czutro, I. Polian, M. Lewis, P. Engelke, S.M. Reddy and B. Becker, “TIGUAN: Thread-parallel Integrated test pattern Generator Utilizing satisfiability ANalysis,” in edaWorkshop, May 2008. Poster.
  • I. Polian, B. Becker and A. Czutro, “Compression Methods for Path Delay Fault Test Pair Sets: A Comparative Study,” in IEEE European Test Symposium, pp. 263-264, May 2004. Poster.